Recent advances in digital communications have led to increased performance demands on transceiver implementations. For a semiconductor transceiver, such increased performance demands may require, for example, higher clock speeds, better heat dissipation, higher density of external connectors, or concurrent use of chips using different semiconductor materials (e.g., silicon germanium, indium phosphide and gallium arsenide).
In one chip assembly technique used to meet the increased performance requirements, a silicon germanium (SiGe) die is bonded to a substrate by the circuit side surface of the die. A heat sink is attached to the opposite side for heat dissipation. Because the die is “flipped” from its conventional “circuit-side up” position, this technique is sometimes called a “flip-chip” configuration.
One operational problem faced by a flip-chip configuration is that when the flip-chip is placed in the same chip assembly with another die that is not in a flip-chip configuration, the two dies generally cannot share a common heat sink. Because one chip is in a “straight up” configuration while the other is in a flip-chip configuration, their heat is dissipated in different directions, thereby making it harder to dissipate the heat by the same heat sink. Such a problem may arise, for example, in a multi-mode chip assembly, wherein the flip-chip may be a silicon germanium die and the “straight up” die may be an indium phosphide or gallium arsenide die that is typically not flipped due to brittleness.
In certain aspects of the disclosure, a better chip assembly is needed to meet the increased performance requirements.